The current method of circuit design is to create logic circuits and array circuits which operate at a specific power level. There are numerous teachings in the art of circuits used to maintain a specific power level or specific current level within a logic gate. In particular, current switch technology has additional circuitry on the chip to minimize current level changes within the logic gate while temperature, power supplies, and lot to lot processes vary. FIG. 1 shows a typical logic speed power curve with an arrow showing the current design practice--pick a power level, maintain the power level and accept the resulting circuit speed (gate delay). The design problem is trying to minimize the performance changes under a variety of conditions. The gate delay versus power curve in FIG. 1 can move in any direction and even change slope. At the same time, the power regulating circuitry has its own perturbations. These result in a wide distribution of logic gate speeds.
FIG. 2 shows a gate delay versus power curve used to illustrate the preferred design technique in accordance with the invention. The speed or delay of the logic gate is selected and the power within the circuit is adjusted to achieve this speed. This is accomplished by designing on chip circuitry sensitive to the transient performance characteristics of the on chip logic or array circuits. This special circuitry (delay regulator) will generate a signal indicative of the chip performance (speed vs. power characteristic) to be compared to a system wide periodic reference signal or clock. The comparison creates a signal which controls the power in the logic and/or array circuitry on chip thereby controlling the performance. [Namely, the point on gate delay versus power curve which corresponds to a fixed gate delay]. By connecting the reference signal to all of the chips in the system, all of the chips will have the same relative performance, i.e. gate delay or speed. Since this is a continuous comparison between the reference signal and the on chip signal, many variables affecting performance, such as power supply, temperature changes, chip to chip process variations, etc. will be minimized or eliminated.
With reference to U.S. patent numbers and publications, a number of prior art disclosures and teachings in the field of integrated circuits are briefly discussed hereinafter.
Reference is made to U.S. Pat. No. Re. 29,619 entitled "Constant-Current Digital-to-Analog Converter" granted Apr. 25, 1978, to J. J. Pastoriza. The Pastoriza patent discloses a digital-to-analog converter the output circuit of which comprises a set of switching transistors arranged as current generators. The currents through the switching transistors are maintained constant by means of a supply voltage adjusting circuit comprising a separate reference transistor matched to one of the switching transistors and energized by the same voltage supply lines as the switching transistors. The supply voltage adjusting circuit includes an operational amplifier which senses the collector current of the reference transistor, and adjusts the supply voltage so as to maintain that collector current constant. This automatic adjustment of the supply voltage also maintains the current through the switching transistors constant.
Reference is made to U.S. Pat. No. 3,602,799 entitled "Temperature Stable Constant Current Source" granted Aug. 31, 1971 to F. J. Guillen. The Guillen patent discloses an ultrastable high speed constant DC current source for generating a precise reference voltage in other apparatus such as a high-speed analogue to digital converter. A continuous constant load current is selectively switched between two current paths, one of which comprises an output load across which said reference voltage is developed. A high-speed digitally controlled driver circuit including a differential amplifier configuration controls the flow of the constant current selectively through one of two hot carrier diodes. The diodes serve as electronic switches from the constant current source which comprises an operational amplifier connected in a feedback loop including a Darlington transistor configuration and controlled by an extremely applied input reference voltage and an error signal developed by the flow of said load current across a temperature compensated resistor.
Reference is made to U.S. Pat. No. 3,743,850 entitled "Integrated Current Supply Circuit" granted July 3, 1973 to W. F. Davis. In the Davis patent, DC biasing currents for a monolithic integrated circuit are obtained from a single regulated current reference source applying current through first and second series connected diodes to establish points of reference potential. Some of the current source transistors which are referenced to this regulated current source have the base-emitter junctions thereof connected across the first diode, and the emitter current of these current source transistors is collected and added to the current from the regulated current source and supplied through the second diode. This second diode, with a larger regulated current flowing therethrough is used to reference additional current without necessitating the use of high ratio area scaling of the emitter areas of these current source transistors.
Reference is made to U.S. Pat. No. 3,754,181 entitled "Monolithic Integrable Constant Current Source For Transistors Connected As Current Stabilizing Elements" granted Aug. 21, 1973 to W. Kreitz et al. The Abstract of the Kreitz et al. patent reads as follows:
"To reduce sensitivity to battery voltage variation in a multiple transistor monolithically integrated constant current source, the control transistor is replaced by an amplifier. Only a fraction of the sum of base currents of the source transistors is applied to the input of the amplifier. Also, the number of source transistors is not as limited by current gain factor as it is when a control transistor is used." PA1 (1) "Current Source Generator" by G. Keller et al. Vol. 12, No. 11, April 1970, page 2031; PA1 (2) Precision Integrated Current Source" by A. Cabiedes et al., Vol. 13, No. 6, November 1970, page 1699; PA1 (3) "Voltage Reference Buffer" by J. A. Dorler et al., Vol. 14, No. 7, December 1971, page 2095; PA1 (4) "Adjustable Underfrequency-Overfrequency Limiting Circuit" by W. B. Nunnery, Vol. 15, No. 6, November 1972, pages 1927-9; PA1 (5) "Reference Voltage Generator and OFF-Chip Driver For Current Switch Circuit" by A. Brunin, Vol. 21, No. 1, June 1978, pages 219-20; and PA1 (6) "Gated Current Source" By J. W. Spencer Jr., Vol. 21, No. 7, December 1978, pages 2719-20. PA1 (1) "Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design 6, Mar. 15, 1974, pages 28 and 30. PA1 (2) "I.sup.2 L Puts It All Together For 10-bit A-D Converter Chip" by Paul Brokaw, Electronics, Apr. 13, 1978, pages 99-105.
Reference is made to U.S. Pat. No. 3,758,791 entitled "Current Switch Circuit" granted Sept. 11, 1973 to K. Taniguchi et al. The Taniguchi et al. patent discloses a current switch circuit consisting of a couple of transistors, one transistor acting as a reference element and the other as an input element a pair of series connections of a resistant element and a diode being connected between the respective collectors of the said transistors with the polarity of the diodes opposite to each other, so that the emitter current of the transistors are automatically regulated to maintain a predetermined value, whereby the DC levels of the output voltages of the current switch circuit are kept constant against temperature variation of the transistors.
Reference is made to U.S. Pat. No. 3,778,646 entitled "Semiconductor Logic Circuit" granted Dec. 11, 1973 to A. Masaki. The Masaki patent discloses a current mode type semiconductor logic circuit comprising at least one grounded-emitter transistor through which a power source is connected to the logic circuit. The output of the logic circuit is fed back to the grounded-emitter transistor through a feedback circuit. As a result, the variation in the output of the logic circuit can be controlled to a minimum even when the load of the logic circuit is varied.
Reference is made to U.S. Pat. No. 3,794,861 entitled "Reference Voltage Generator" granted Feb. 26, 1974 to J. R. Bernacchi. The Bernacchi patent discloses a reference voltage generator circuit particularly suited for current source circuits having low temperature sensitivity and low voltage sensitivity. The circuit is comprises of a reference voltage circuit having low voltage sensitivity and relatively high temperature sensitivity, with an additional feedback circuit for feeding back a compensating temperature sensitivity to result in a low overall sensitivity. The temperature sensitivity of the reference generator is predominately due to the temperature sensitivity of a base to emitter diode voltage drop which may be selectively controlled or substantially cancelled by the proper selection of resistors in the feedback circuit so as to feed back a temperature sensitive component. The feedback signal is dependent upon the difference in the base to emitter voltage drops in two transistors conducting different magnitudes of current, and is similarly amplified so as to effectively allow cancellation of the basic reference generator sensitivity.
Reference is made to U.S. Pat. No. 3,803,471 entitled "Variable Time Ratio Control Having Power Switch Which Does Not Require Current Equalizing Means" granted Apr. 9, 1974 to R. G. Price et al. The Price et al. patent discloses a pulse width modulation control having a power switch arrangement which does not require external current equalization means has a plurality of paralleled power transistors whose forward current transfer ratio decreases abruptly with increase in collector current and whose base drive is supplied by a constant current switching regulator having a plurality of paralled clamping transistors in shunt to the regulator output terminals which are turned on by variable width pulses to shunt current away from the power transistors and thereby turn the power switch off and on. The regulator output is coupled to the base of each power transistor by a diode whose forward drop promotes base current sharing and which prevents multiple transistor failure.
Reference is made to U.S. Pat. No. 3,808,468 entitled "Bootstrap FET Driven With ON-Chip Power Supply" granted Apr. 30, 1974 to P. J. Ludlow et al. The Ludlow et al. patent discloses a bootstrap FET driver amplifier having a precharged relatively higher gate voltage and a relatively lower drain voltage obtained from a common power source. The gate voltage is derived from recurrent pulses produced by an on-chip FET free-running multi-vibrator and a voltage amplifier circuit powered from said power source. The pulse width of the recurrent pulses varies as an inverse function of the transconductance of the on-chip FETs and as a direct function of the threshold voltage of the on-chip FETs. The pulse width controls the charging time of a voltage booster capacitor in the voltage multiplier circuit whereby the amplitude of the boosted voltage is a direct function of the pulse width. The boosted voltage is applied to the gate of the bootstrap FET driver amplifier.
Reference is made to U.S. Pat. No. 3,978,473 entitled "Integrated-Circuit Digital to Analog Converter" granted Aug. 31, 1976 to J. J. Pastoriza. The Pastoriza patent discloses a digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example, in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.
Reference is made to U.S. Pat. No. 4,004,164 entitled "Compensating Current Source" granted Jan. 18, 1977 to H. C. Cranford. The Cranford patent discloses a circuit to provide a current source for use on a semiconductor chip having field effect transistors (FET) deposited therein to compensate for variations in the substrate voltage source. Analog type circuits when alone on a semiconductor chip or combined with digital type logic circuits are normally susceptible to disturbances in the bias voltage applied to the substrate of the chip. The obtaining of a uniform output response from an analog type circuit due to an input voltage change has heretofore required the use of off-chip precision voltage sources. Such expensive precision sources can be eliminated and normally variable (+15%) supplies can be used by providing an on-chip compensating current source which combines with other circuits to provide stable reference voltage levels on the chip for use by the analog circuits.
The compensating circuit comprises two depletion type field effect transistors (FET) in series between a higher voltage source and the substrate voltage, the FET connected to the higher voltage having its gate connected to the common node between the transistors and being in saturation and the lower voltage one having its gate connected to a ground voltage and being conductive in its linear region. An enhancement type transistor has its gate connected to the common node of the two depletion FETs and its source connected to the negative side of the substrate voltage source. By a proper selection of parameters, this circuit will pass a current varying inversely with changes in the substrate supply voltage to provide a compensated current source for other analog circuits. Representative circuits are shown for a stabilized voltage reference, for a differential amplifier current control and a combined circuit.
Reference is made to U.S. Pat. No. 4,029,974 entitled "Apparatus for Generating A Current Varying With Temperature" granted June 14, 1977 to A. P. Brokaw. The Brokaw patent discloses a digital-to-analog converter of the type formed with a plurality of current source transistors arranged to carry different levels of current according to a predetermined weighting pattern, e.g., a binary weighting pattern. In the converter, a plurality of identically sized current source transistors carry the different levels of current and thus operate at different current densities with different base-to-emitter voltages subject to temperature drift. Stable emitter voltages, providing accurate levels of weighted current, are developed by means of resistances between the bases of successive current source transistors and a current source for developing across the interbase resistances a voltage linearly varying with absolute temperature, corresponding to the difference between base-to-emitter voltages of the successive current source transistors.
The apparatus for generating a current linearly varying with absolute temperature is formed with first and second transistors forced to carry the same current at different current densities to produce different base-to-emitter voltages, and means such as an emitter resistor responsive to the difference in the base-to-emitter voltages for developing a current, corresponding to the difference in base-to-emitter voltages, which varies linearly with temperature.
Reference is made to U.S. Pat. No. 4,100,431 entitled "Integrated Injection Logic to Linear High Impedance Current Interface" granted July 11, 1978 to J. J. Stipanuk. The Stipanuk patent discloses an interface circuit for interconnecting an integrated injection logic (I.sup.2 L) portion of an integrated circuit to a linear portion of an integrated circuit. The circuit transfers both logic information and I.sup.2 L current level references from the I.sup.2 L circuitry to the linear circuitry at the relatively large voltage levels present in linear circuitry. One embodiment employs a cascode arrangement involving one transistor, two diodes and a resistor. Another embodiment utilizes the matching characteristics of a pair of transistors operating in the forward and reverse modes respectively to perform the function with only one transistor.
Reference is made to U.S. Pat. No. 4,145,621 entitled "Transistor Logic Circuits" granted Mar. 20, 1979 to S. F. Colaco. The Colaco patent discloses a transistor logic circuit including a constant current source in the form of a current mirroring arrangement connected to a logical gating combination of switching transistors, the arrangement being such that the switching transistors do not saturate.
Reference is made to U.S. Pat. No. 4,160,934 entitled "Current Control Circuit For Light Emitting Diode" granted July 10, 1979 to H. C. Kirsch. In the Kirsch patent, the current in a semiconductive light emitting diode (LED), driven by an insulated gate field effect transistor (IGFET) switch, is stabilized by a current control circuit including a comparator type feedback network, which stabilizes the voltage at a node located between said switch and the series connection of a ballast resistor and the LED.
Reference is made to U.S. Pat. No. 4,172,992 entitled "Constant Current Control Circuit" granted Oct. 30, 1979 to D. D. Culmer et al. In the Culmer et al. patent, a pair of transistors are operated at different current densities so as to develop a differential base to emitter potential. This potential is used as a reference in a negative feedback stabilization circuit which passes a current that is regulated by the potential. The circuit can also regulate the currents flowing in a plurality of additional current sources and sinks connected thereto.
Reference is made to U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit For A Logic Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger et al. The Berger et al. patent discloses basic I.sup.2 L structure and circuitry.
Reference is made to the following IBM Technical Disclosure Bulletin Publications:
Reference is also made to the following publications: